The present invention relates generally to data bus communications, and more specifically to a system where different peripherals on a bus may be characterized by data widths that are different from the width of the data bus.
As computer systems have evolved, the data path has gotten wider. In recognition of the fact that peripheral devices do not always match the system bus width, provision has been made for dynamic bus sizing. For example, the standard PC AT architecture uses a 16-bit data bus (SD-bus), and provides a separate 8-bit bus (XD-bus) for the attachment of 8-bit devices. Similarly, the PS/2's Microchannel architecture uses a 32-bit data path, with provision for attachment of 16-bit devices. Logic on the system board controls bus crossover logic (data swapper) to allow the data on the lower half of the bus to be steered to the upper half of the bus, or vice versa, depending on the particular situation.
Consider, for example, a situation where a 32-bit master addresses a 16-bit slave attached to the lower half of the bus. According to a typical prior art approach, the slave signifies it is a 16-bit device, and provides 16 bits of data on the lower half of the bus. The master then makes a separate request for the other 16 bits, and specifies that it will receive that data on the upper half of the bus. This approach provides the needed flexibility, but suffers from the problem that the master has to make a separate request for the second half of the data, which is costly in terms of bus cycles.